Research project Development of superconducting electronics for in-memory computing

We are leaving in the time of digital revolution. The amount of processed data and corresponding large data centers and computation facilities are increasing in an explosive manner. This causes major problems associated both with ineffectiveness of big-data processing by the standard CPU-centered computer architecture, colloquially known as “the memory wall”, and with the growing energy consumption caused by resistive losses in semiconducting electronics. This has led to a renewed interest in development of a superconducting computer. Zero resistance of superconductors could lead to a drastic increment of the calculation speed and reduction of the consumed power. This can make a significant contribution for reaching sustainable development of society keeping present trends in digitalization. Although a functioning RSFQ superconducting computer architecture has been developed half a century ago, it suffers from a problem of principle un-scalability. Therefore, new approaches and ideas are needed for future generations of superconducting computers. In particular, a paradigm shift from the old CPU-centered to new memory-centered data processing would be required. Within this project we are aiming to develop novel vortex-based superconducting electronic components. We anticipate that such electronics would be scalable to nanometer sizes and would be suitable both for conventional digital (Boolean logics) operations and, even more interestingly, for emerging analog data processing applicable for neuromorphic artificial intelligence and in-memory computation techniques.

The purpose of this project is to develop novel type of superconducting electronic components that would be needed for a future generation of fast and energy-efficient supercomputers with data-centered in-memory architecture. The central idea of our approach is to employ quantized Abrikosov vortices as information carriers.
The aim is to develop three key components: (i) a dense superconducting random-access memory; (ii) reconfigurable logical elements with in-built memory functionality that would facilitate in-memory computation; and (iii) a trainable analog memory element for application in neuromorphic computing.